Mips Branch Delay Slot Instruction


There are 10 branch instructions: BEQ, BNE, BLEZ, BGEZ, BLTZ, BGTZ, J, JAL, JR and JALR. These all update the pc. The MIPS makes use of a branch delay slot to remove the need to flush the pipeline when a branch is taken. In other words, the instruction immediately following a branch will alwaysbeexecutedregardlessof whetherthebranch is takenor. A delay slot can be implemented if desired. With V1.30 a simple branch-target-buffer can also be simulated. A branch instruction indicates that it is predicted as being taken. The full instruction set is not currently implemented. A branch delay slot follows the instruction. Bgt s,t,addr pseudo branch if s t A branch delay slot follows the instruction. Ble s,t,addr pseudo branch if s branch delay slot follows the instruction. Blez s,addr normal branch if the two's comp. Integer in register s is branch delay slot follows the instruction. The load instruction should not be placed in the delay slot as it is a part of the taken branch with an undefined behaviour. The 'sll' was expected to be in the slot. This is a series of unfortunate events that causes this to happen: 1.

(This site is now maintained from here. I no longer work at DCU.)

WinMIPS64 is an instruction set simulator, and is designed as a replacement for the popular Microsoft Windows utility WinDLX. The classic text

from its 3rd edition has switched from the 32-bit DLX architecture, to the 64-bit MIPS architecture. Hence the need for a new teaching tool.WinDLX had a very nice friendly user interface, including a full graphical simulation of the 5-stage pipeline. Therefore it was decided to create a similar tool for the MIPS64 with a very similar interface.


If you know how to use WinDLX then the look-and-feel of WinMIPS64 will be very familiar. However there are a few changes.

  • Forwarding is indicated by colouring the forwarded register. The colour indicates the stage in the pipeline that it is being forwarded from.
  • A delay slot can be implemented if desired. With V1.30 a simple branch-target-buffer can also be simulated. A << in the code window beside a jump or branch instruction indicates that it is predicted as being taken.
  • The full instruction set is not currently implemented. In particular there is no support for single precision floating-point, or 'paired single' floating-point.
  • Registers and memory can be changed by left-double-clicking on the target. Right-double-clicking on memory displays it in double-precision decimal floating point format.
  • Break-points are set and cleared by simply left-double-clicking on the code window.

The software is available for download in a .ZIP archive. This includes the Windows '98/2000/NT/whatever executable, a simple stand-alone DOS assembler, and several example programs. It may be used freely without restriction. If you find any bugs, or would like to see an additional feature, please let me know at[email protected]

Download from WinMIPS64. Documentation in Microsoft Word format is also available. Here are a couple of lab exercises ex2.docand ex3.doc

Full Visual C++ source code is available on request - but tell me who you are and why you want it.

Update History:


  • displays the currently loaded file on status line (press F10).
  • remembers last folder used for input.


  • Bug fix - registers modified by double-clicking stay modified.
  • Integer dmul and ddiv instructions disabled (they make many tutorial problems too easy!)


  • Support for network installations
  • Various minor bug -fixes


  • System far less tolerant of silly syntax errors
  • Open file name appears on title bar.


Mips Branch Delay Slot Instruction
  • Some fonts fixed
  • Possibility of WAR hazards for FP instructions recognized


  • F5 removed
  • Bug in Cycles window fixed


  • Branch Target Buffer option added
  • Minor bugs eliminated
  • More example programs


  • Long lines generate an error
  • Larger data area allowed


  • Standard MIPS pseudo-names for registers now allowed
  • .. so $zero for r0, $t0 for r8 etc. Also $6 for r6.
  • # is now acceptable as well as ; to indicate a comment


  • New Dumb Terminal I/O capability – New Terminal Window
  • New example program testio.s – demos output capability
  • Graphics output capability


  • 10 new instructions!
  • Integer dmul and ddiv instructions restored


·Some bug fixes

Mips Instruction Set Branch Delay Slot


·Errors on pass 2 now highlighted in red.

·Viewing FP memory no longer changes it


Mips Branch Delay Slot Instructions

·Some more bug fixes


·Yet more bug fixes


·LWU/LUI Instructions fixed


·Some WAW error fixed



Mike Scott, April 2012 Da

  • Restricted Project
rGaaac4e0ac6ee: Merging r354672:
rL358920: Merging r354672:
rG6083106b1216: [mips][micromips] fix filling delay slots for PseudoIndirectBranch_MM
rL354672: [mips][micromips] fix filling delay slots for PseudoIndirectBranch_MM

Filling a delay slot in 32bit jump instructions with a 16bit instruction can cause issues. According to documentation such an operation is unpredictable. Multiple test from test-suite that fail on microMIPS show this spot as source of failure. This patch adds opcode Mips::PseudoIndirectBranch_MM alongside Mips::PseudoIndirectBranch and other instructions that are expanded to jr instruction and do not allow a 16bit instruction in their delay slots.

Event Timeline

mbrkusanin created this revision.Feb 21 2019, 7:30 AM
Herald added subscribers: arichardson, sdardis. · View Herald TranscriptFeb 21 2019, 7:30 AM
sdardis accepted this revision.Feb 21 2019, 11:17 AM
Comment Actions

LGTM apart from some minor nits. Please address them before committing.

1 ↗(On Diff #187792)

Drop the '--check-prefixes=MIPS'. Also use the update_llc_checks.py script.

2 ↗(On Diff #187792)

Add a quick description of the purpose of this test is, i.e. 'Test that the delay slot filler correctly handles indirect branches for microMIPS.'

5 ↗(On Diff #187792)

These check lines can be removed, just rely on the update_llc_checks.py script.

16 ↗(On Diff #187792)
This revision is now accepted and ready to land.Feb 21 2019, 11:17 AM
sdardis added a subscriber: llvm-commits.Feb 21 2019, 1:47 PM
Comment Actions

Sorry I didn't spot this earlier, but in future please ensure 'llvm-commits' is one of the subscribers when creating a review request for LLVM. If you add it after creating a review request, manually add it and write something in the comments field to trigger Phabricator into sending an email or abandon the review request and re-open it with the relevant -commits list as an initial subscriber.

Posting review requests without the relevant -commits list means that only the subscribers added, subscribers added through Herald rules and initial reviewers will see the request. It is policy that patches are emailed to the relevant list for review[1]. Submitting patches through Phabricator is fine, provided the relevant -commits list is in the subscribers.


[1] http://www.llvm.org/docs/DeveloperPolicy.html#making-and-submitting-a-patch

mbrkusanin updated this revision to Diff 187927.Feb 22 2019, 4:59 AM
Comment Actions
mbrkusanin marked 5 inline comments as done.Feb 22 2019, 5:01 AM
Closed by commit rL354672: [mips][micromips] fix filling delay slots for PseudoIndirectBranch_MM (authored by petarj). · Explain WhyFeb 22 2019, 6:55 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 22 2019, 6:55 AM
Herald added a subscriber: jrtc27. · View Herald Transcript
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